Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2405991
date_generatedSun Apr 21 18:17:20 2019 os_platformWIN64
product_versionVivado v2018.3 (64-bit) project_idb12f7928464443dbbe1efc1a5b61a76a
project_iteration24 random_idbeb9ff36c311502b98a6bfa1061e73bf
registration_idbeb9ff36c311502b98a6bfa1061e73bf route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD Ryzen Threadripper 1950X 16-Core Processor cpu_speed3394 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram68.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=12 addrepositoryinfodialog_ok=13 addrepositoryinfodialog_repository_tree=13 addsrcwizard_specify_or_create_constraint_files=1
basedialog_apply=2 basedialog_cancel=27 basedialog_ok=160 basedialog_yes=12
basereporttab_rerun=10 boardchooser_board_table=1 cmdmsgdialog_messages=15 cmdmsgdialog_ok=61
commandsinput_type_tcl_command_here=1 constraintschooserpanel_add_files=1 coretreetablepanel_core_tree_table=35 createnewdiagramdialog_design_name=4
creatersbportdialog_create_vector=4 creatersbportdialog_direction=8 creatersbportdialog_from=2 creatersbportdialog_port_name=15
duplicateipwarndialog_add_active_ip=2 filesetpanel_file_set_panel_tree=247 flownavigatortreepanel_flow_navigator_tree=133 gettingstartedview_create_new_project=1
hcodeeditor_search_text_combo_box=12 hpopuptitle_close=7 ipstatussectionpanel_upgrade_selected=24 ipstatustablepanel_ip_status_table=16
ipstatustablepanel_more_info=4 launchpanel_generate_scripts_only=1 launchpanel_launch_runs_on_local_host=1 logmonitor_monitor=1
mainmenumgr_checkpoint=11 mainmenumgr_edit=2 mainmenumgr_export=14 mainmenumgr_file=30
mainmenumgr_floorplanning=1 mainmenumgr_flow=7 mainmenumgr_help=2 mainmenumgr_io_planning=1
mainmenumgr_ip=11 mainmenumgr_project=14 mainmenumgr_reports=24 mainmenumgr_text_editor=11
mainmenumgr_timing=1 mainmenumgr_tools=77 mainmenumgr_view=4 mainmenumgr_window=15
maintoolbarmgr_open=1 maintoolbarmgr_run=4 mainwinmenumgr_layout=12 messagewithoptiondialog_dont_show_this_dialog_again=3
msgtreepanel_message_view_tree=36 msgview_clear_messages_resulting_from_user_executed=4 netlisttreeview_netlist_tree=2 numjobschooser_number_of_jobs=3
pacommandnames_add_config_memory=4 pacommandnames_add_sources=4 pacommandnames_auto_connect_target=9 pacommandnames_auto_update_hier=29
pacommandnames_create_top_hdl=1 pacommandnames_customize_rsb_bloc=10 pacommandnames_goto_implemented_design=1 pacommandnames_goto_netlist_design=1
pacommandnames_goto_source=3 pacommandnames_ip_packager_wizard=1 pacommandnames_ip_settings=1 pacommandnames_language_templates=2
pacommandnames_launch_hardware=4 pacommandnames_open_project=2 pacommandnames_open_target_wizard=1 pacommandnames_program_fpga=4
pacommandnames_regenerate_layout=1 pacommandnames_report_ip_status=6 pacommandnames_reports_window=4 pacommandnames_run_bitgen=1
pacommandnames_run_implementation=1 pacommandnames_run_synthesis=1 pacommandnames_set_as_top=2 pacommandnames_validate_rsb_design=1
pacommandnames_write_config_memory_file=1 pacommandnames_zoom_out=1 paviews_code=1 paviews_ip_catalog=1
paviews_project_summary=19 planaheadtab_refresh_changed_modules=11 planaheadtab_refresh_ip_catalog=13 programdebugtab_open_target=2
programdebugtab_program_device=20 programdebugtab_refresh_device=1 programfpgadialog_program=33 progressdialog_background=24
progressdialog_cancel=2 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1 quickhelp_help=4
rdicommands_copy=1 rdicommands_custom_commands=34 rdicommands_delete=18 rdicommands_properties=3
rdicommands_settings=28 rsbaddmoduledialog_hide_incompatible_modules=4 rsbaddmoduledialog_module_list=5 rsbapplyautomationbar_run_connection_automation=4
saveprojectutils_save=15 selectmenu_highlight=22 settingsdialog_project_tree=29 settingsprojectiprepositorypage_add_repository=17
settingsprojectiprepositorypage_refresh_all=16 settingsprojectiprepositorypage_repository_chooser=25 simpleoutputproductdialog_close_dialog_unsaved_changes_will=10 simpleoutputproductdialog_generate_output_products_immediately=16
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=5 srcmenu_ip_hierarchy=33 srcmenu_open_selected_source_files=2 srcmenu_refresh_hierarchy=1
stalemoreaction_force_up_to_date=1 stalemoreaction_out_of_date_details=2 statemonitor_reset_run=1 syntheticastatemonitor_cancel=2
systembuildermenu_add_ip=1 systembuildermenu_add_module=6 systembuildermenu_create_port=12 systembuildermenu_ip_documentation=45
systembuilderview_add_ip=19 systembuilderview_orientation=46 systembuilderview_pinning=64 systemtab_report_ip_status=2
systemtab_show_ip_status=4 systemtreeview_system_tree=44 taskbanner_close=8 tclconsoleview_tcl_console_code_editor=1
touchpointsurveydialog_no=2
java_command_handlers
addsources=10 autoconnecttarget=9 coreview=1 createblockdesign=6
createtophdl=1 customizersbblock=16 editcopy=3 editdelete=58
editpaste=3 editproperties=3 editundo=4 ippackagerwizardhandler=1
launchprogramfpga=34 newlaunchhardware=4 newproject=1 openblockdesign=15
openhardwaremanager=24 openproject=2 openrecenttarget=17 programdevice=16
refreshdevice=1 regeneratersblayout=1 reportipstatus=8 runbitgen=45
runimplementation=4 runsynthesis=3 settopnode=1 showsource=4
showview=23 toolssettings=31 toolstemplates=2 upgradeip=23
validatersbdesign=1 viewtaskimplementation=7 viewtaskipintegrator=1 zoomout=1
other_data
guimode=10
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=8 export_simulation_ies=8
export_simulation_modelsim=8 export_simulation_questa=8 export_simulation_riviera=8 export_simulation_vcs=8
export_simulation_xsim=8 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=4 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=9 totalsynthesisruns=9

unisim_transformation
post_unisim_transformation
bufg=7 carry4=74 dsp48e1=2 fdre=689
fdse=75 gnd=20 ibuf=6 lut1=75
lut2=170 lut3=135 lut4=134 lut5=58
lut6=94 mmcme2_adv=1 obuf=1 obufds=4
srl16e=2 srlc32e=2 vcc=19
pre_unisim_transformation
bufg=7 carry4=74 dsp48e1=2 fdre=689
fdse=75 gnd=20 ibuf=6 lut1=75
lut2=170 lut3=135 lut4=134 lut5=58
lut6=94 mmcme2_adv=1 obuf=1 obufds=4
srl16e=2 srlc32e=2 vcc=19

ip_statistics
HDMI_test/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=HDMI_test x_ipproduct=Vivado 2018.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
IP_Integrator/1
bdsource=USER core_container=NA da_board_cnt=1 da_clkrst_cnt=2
iptotal=1 maxhierdepth=0 numblks=8 numhdlrefblks=5
numhierblks=0 numhlsblks=2 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=8 numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VERILOG
x_iplibrary=BlockDiagram x_ipname=Testing_HDMI x_ipvendor=xilinx.com x_ipversion=1.00.a
Interface/1
core_container=NA iptotal=1 x_ipcorerevision=1904211809 x_iplanguage=VERILOG
x_iplibrary=hls x_ipname=Interface x_ipproduct=Vivado 2018.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
clk_wiz_v6_0_2_0_0/1
clkin1_period=8.000 clkin2_period=10.0 clock_mgr_type=NA component_name=Testing_HDMI_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=5 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
hls_ip_2018_3/1
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=1
hls_input_float=0 hls_input_part=xc7z020clg400-1 hls_input_type=cxx hls_syn_clock=2.763500
hls_syn_dsp=0 hls_syn_ff=0 hls_syn_lat=0 hls_syn_lut=19
hls_syn_mem=0 hls_syn_tpt=none hls_version=2018_3 iptotal=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-16=30 timing-6=6

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") clocks=0.007160 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Medium
confidence_level_overall=Medium customer=TBD customer_class=TBD devstatic=0.109574
die=xc7z020clg400-1 dsp_output_toggle=12.500000 dynamic=0.245331 effective_thetaja=11.5
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=0.134971 input_toggle=12.500000 junction_temp=29.1 (C)
logic=0.000484 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 mmcm=0.105909 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.354905 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=clg400 pct_clock_constrained=1.000000 pct_inputs_defined=50 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.000387 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=7.4 (C/W)
thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.5
user_junc_temp=29.1 (C) user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.058734
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.010887 vccaux_total_current=0.069621 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000490 vccbram_total_current=0.000490 vccbram_voltage=1.000000 vccint_dynamic_current=0.005365
vccint_static_current=0.008243 vccint_total_current=0.013609 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.040680
vcco33_static_current=0.001000 vcco33_total_current=0.041680 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000
vcco_ddr_static_current=0.000000 vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000
vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000
vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000
vccpaux_static_current=0.010330 vccpaux_total_current=0.010330 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000
vccpint_static_current=0.017950 vccpint_total_current=0.017950 vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000
vccpll_static_current=0.003000 vccpll_total_current=0.003000 vccpll_voltage=1.800000 version=2018.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=25.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=3 fdre_functional_category=Flop & Latch fdre_used=114
fdse_functional_category=Flop & Latch fdse_used=10 ibuf_functional_category=IO ibuf_used=2
lut1_functional_category=LUT lut1_used=3 lut2_functional_category=LUT lut2_used=18
lut3_functional_category=LUT lut3_used=61 lut4_functional_category=LUT lut4_used=33
lut5_functional_category=LUT lut5_used=37 lut6_functional_category=LUT lut6_used=61
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 obuf_functional_category=IO obuf_used=1
obufds_functional_category=IO obufds_used=4
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=148 lut_as_logic_util_percentage=0.28
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=124 register_as_flip_flop_util_percentage=0.12
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=148 slice_luts_util_percentage=0.28
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=124 slice_registers_util_percentage=0.12
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=148 lut_as_logic_util_percentage=0.28 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=5 lut_in_front_of_the_register_is_used_fixed=5 lut_in_front_of_the_register_is_used_used=28
register_driven_from_outside_the_slice_fixed=28 register_driven_from_outside_the_slice_used=33 register_driven_from_within_the_slice_fixed=33 register_driven_from_within_the_slice_used=91
slice_available=13300 slice_fixed=0 slice_registers_available=106400 slice_registers_fixed=0
slice_registers_used=124 slice_registers_util_percentage=0.12 slice_used=45 slice_util_percentage=0.34
slicel_fixed=0 slicel_used=33 slicem_fixed=0 slicem_used=12
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_used=6 unique_control_sets_util_percentage=0.05
using_o5_and_o6_fixed=0.05 using_o5_and_o6_used=65 using_o5_output_only_fixed=65 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=83
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=Testing_HDMI_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:23s hls_ip=0 memory_gain=516.266MB memory_peak=805.238MB